1) Field of the Invention
The present invention relates to a technique for maintaining records of data in an SRAM (Static Random Access Memory).
2) Description of the Related Art
DRAMs (Dynamic Random Access Memories) store data with electric charges, but the electric charges decrease (leak out) with the passage of time. Accordingly, DRAMs require so-called refreshing by reading out data within a predetermined time period to restore the electric charge, in order to prevent the electric charge charged in a capacitor from leaking out.
To the contrary, SRAMs (Static Random Access Memory), which are nonvolatile memories, do not require refreshing.
As shown in FIG. 4, an SRAM cell (memory cell) 100 having six transistors includes a bistable latch, it thus does not require refreshing because the electric charge does not leak.
Meanwhile, an SRAM having a DRAM structure as disclosed in a patent document 1 below requires refreshing.
Heretofore known are soft errors caused by an alpha ray and a neutron occurring in DRAMs and SRAMs.
As the soft error caused by an alpha ray or a neutron, positive holes and electrons generated when the alpha ray passes through a silicon chip 101 dissipate an electric charge (an electric charge stored in a capacitor 102 in the drawing; for example, 40 to 50 fc) relating to storage of data to cause inversion of the data, as shown in FIG. 5. Incidentally, the silicon chip 101 shown in FIG. 5 is a DRAM.
Since the soft error caused by an alpha ray occurs instantly, it cannot be prevented. However, an effort to remove an alpha ray source involved in the package of an SRAM or DRAM has been made, which has reached a level in recent years where the soft error is overcome in practical use if the data is corrected with ECC (Error Checking and Correction; Error Correction code).
To the contrary, the soft error caused by a neutron in an SRAM or DRAM occurs in such a way that collision of the neutron with an atomic nucleus of silicon causes a nuclear reaction as shown in FIG. 5, which generates electrons and positive holes along its trajectory at this time. Such electrons and positive holes cause loss or inversion of the electric charge of the capacitor 102. Incidentally, an amount of electric charge generated by an alpha ray is approximately 16 fC/μm, whereas an amount of electric charge generated by a neutron is approximately 160 fC/μm, as shown in FIG. 5.
The soft error caused by a neutron cannot be prevented because it originates from cosmic rays, thus the soft error has been dealt with ECC as temporary measures.
It is generally said that the amount of neutrons reaching the ground in Tokyo is 11.66 to 8.42/cm2 per hour.
The above-mentioned soft error caused by a neutron not only occurs in a single memory cell but also causes multi-bit error where electric charges of plural memory cells are lost, which often cannot be corrected with ECC.
As a result of verification of various experiments, the applicant of this application gave attention to differences in behavior between a soft error caused by a neutron and a soft error caused by an alpha ray in SRAMs. One of these is a latch-up phenomenon which never occurs in the soft error caused by an alpha ray because the energy of a neutron (that is, an amount of electric charge generated by a neutron) is large.
The latch-up phenomenon occurs because of a thyristor structure parasitically existing due to a CMOS (Complementary Metal Oxide Semiconductor) structure 103 in a memory cell of an SRAM configured as shown in FIG. 6. Unlike the soft error caused by an alpha ray, the latch-up phenomenon does not directly destruct stored data.
As shown in FIG. 7, in the CMOS structure 103 which is a memory cell structure of an SRAM, an NPN parasitic transistor Tr1, a PNP parasitic transistor Tr2 and diffused resistors R1 to R4 exist, by which a thyristor structure S shown in FIG. 8 is formed.
An electric charge generated by collision of a neutron with an atomic nucleus triggers the thyristor structure S to activate the same, which generates a current path between the power source (Vdd) and the ground of the thyristor structure S (that is, generates the latch-up phenomenon). This destructs the data, as a result.
More concretely, when electric current flows from the diffused resistor (hereinafter referred simply as a resistor) R2 to the resistor R4 due to collision of a neutron, for example, the parasitic transistor Tr1 is turned ON. Pulled by the electric current flowing from the resistor R2 to the resistor R4, electric current flows from the power source Vdd to the resistor R3, whereby the parasitic transistor Tr2 is turned ON. As a result, a path of the electric current flowing from the power source Vdd to the ground (denoted as “GND” in the drawing) through the parasitic transistor Tr2, the resistor R3 and the parasitic transistor Tr1 is established, whereby the electric current leaks.
This leaking electric current causes loss of the electric charge in the memory cell, causing destruction of the data.
Moreover, once a path between the power source Vdd and the ground is established, the leaking electric current keeps flowing. This causes destruction of data in not only a single cell but also other memory cells, which leads to a multi-bit error.
Unlike the soft error caused by an alpha ray, data destruction caused by the latch-up phenomenon does not occur instantaneously, but the latch-up phenomenon destructs data with a predetermined time constant because the thyristor structure parasitically exists because of the memory cell structure of an SRAM which involves the diffused resistors R1 through R4.
As above, the applicant of the present application found that the latch-up phenomenon, which cannot be corrected by ECC, destructs the data as the soft error due to a neutron in an SRAM, and clarified its mechanism.
[Patent Document] Japanese Unexamined patent application Publication Ser. No. 2003-208787